The present application relates generally to integrated circuit (IC) chips, and more particularly to a dielectric cap for use with a back-end-of-the-line (BEOL) interconnect structure, especially a BEOL interconnect structure including Cu embedded within an ultra-low k dielectric constant dielectric material.
Generally, semiconductor devices include a plurality of circuits which form an IC fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the elements distributed on the surface of the semiconductor substrate. Efficient routing of these signals across the device requires the formation of multilevel or multilayered schemes, such as, for example, single and dual damascene interconnect structures. Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate, while metal lines run parallel to the semiconductor substrate.
In traditional interconnect structures, aluminum and aluminum alloys have been used as interconnect metallurgies for providing electrical connections to and from devices in BEOL layers of the devices. While aluminum-based metallurgies have been the material of choice for use as metal interconnects in the past, aluminum no longer satisfies requirements as circuit density and speeds for IC chips increase and the scale of the devices decrease to nanometer dimensions. Thus, copper and copper alloys are being employed as a replacement for aluminum-based metallurgy in nano electronic devices because Cu-based metallurgies have lower resistivity and lower susceptibility to electromigration failure as compared to aluminum-based metallurgies.
One challenge to using copper-based metallurgies is that copper diffuses readily into the surrounding dielectric material as processing steps continue. To inhibit copper diffusion, copper-containing interconnects can be isolated by employing protective barrier layers. Such barrier layers include, for example, conductive diffusion barrier liners of tantalum, titanium or tungsten, in pure form, alloyed form or nitride form. These traditional barrier layers are located along the sidewalls and bottom of the copper-containing interconnect structure.
In addition to using such conductive diffusion barrier liners, capping layers are typically disposed on at least the copper surface of the interconnect structure. Dielectric capping layers such as, for example, silicon nitride, have been most commonly used to cap the upper surface of the metal interconnect structure. Recently, inorganic capping layers including, for example, CoWP, have been used as the metal interconnect capping layer.
A conventional interconnect structure utilizing copper metallization and capping layers as described above typically includes a lower substrate which may contain logic circuit elements such as transistors. An interlevel dielectric (ILD) overlies the substrate. The ILD in past interconnect structures was typically comprised of silicon dioxide. However, in more recent and advanced interconnect structures, the ILD is preferably a SiCOH dielectric or polymeric thermoset material having a dielectric constant of less than or equal to 3.0.An adhesion promoter may be disposed between the substrate and the ILD. A hard mask such as, for example, a silicon nitride hard mask, can optionally be formed atop the ILD. The hard mask may also be referred to as a polish stop layer. At least one conductive material is embedded within the ILD. The conductive material is typically copper in advanced interconnect structures, but alternatively may be aluminum or other conductive materials. When the conductive material is copper, a diffusion barrier liner, as discussed above, is typically disposed between the ILD and the copper metallurgy.
An upper surface of conductive material is typically made coplanar with an upper surface of the hard mask, if present, or the upper surface of the ILD, if the hard mask is not present. A capping layer, as mentioned above, is then typically disposed on the conductive material and either the hard mask, if present, or the ILD, if the hard mask is not present. The capping layer acts as a diffusion barrier to prevent diffusion of the conductive material such as Cu into the surrounding ILD.
High density plasma (HDP) chemical vapor deposition (CVD) capping layers provide superior electromigration protection, as compared to plasma enhanced (PE) CVD films, because HDP CVD films more readily stop the movement of metallic atoms, e.g., copper atoms, along the interconnect surface in the capping layer.
Recently, the use of ultra low dielectric constant dielectric materials (i.e., k equal to or less than 3.0) for BEOL interconnects has turned to low k two phase porous SiCOH or polymeric thermoset dielectric materials. These dielectric materials require the use of a post curing step using ultraviolet (UV) or electron beam (E-Beam) radiation. This post cure UV radiation, for example, causes tensile stress change in the capping layer. In particular, UV exposure changes the stress of most prior art capping layers from compressive stress, which is preferred, to tensile stress, which is less preferred. Moreover, UV exposure causes prior art capping layers to crack and an adhesion problem between the capping layer and the ultra low dielectric constant dielectric material may arise. Any crack in the capping layer may lead to metallic diffusion into the ILD layer through the seam leading to formation of a metallic nodule under the capping layer. Such a metallic nodule may lead to short circuits due to leakage of current between adjacent interconnect lines.
UV and/or E-beam radiation may also cause other damage such as, for example, increased tensile stress, delamination and blister formation over patterned interconnect lines, particularly during subsequent dielectric depositions, metallization, and chemical-mechanical polishing. Furthermore, the need for reducing capacitance in advanced nano electronic devices also requires that the overall dielectric constant of the capping layer be lowered below that of silicon nitride (k˜7.0) and silicon carbon nitride (SiCN, k˜5.5) capping layers.
Additionally, the use of an ultra-low k porous p-SiCOH ILD, which is a mostly tensile dielectric film, requires that the capping layer must maintain a high compressive stress, to balance out the tensile force in thicker p-SiCOH ILD, as-deposited and upon subsequent UV/E-beam/thermal processing steps. Furthermore, the deposition of these capping layers must not cause any subsequent chemical or electrical damage to the ultra low dielectric constant dielectric materials and metal surfaces that are in contact with the capping layers. Otherwise, the damage to the ultra low dielectric constant dielectric materials and metal surfaces may cause degradation in subsequent fabrication steps and process integration control, in device's performance, yields and reliability.